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MTB50P03HDL
Preferred Device
Power MOSFET 50 Amps, 30 Volts, Logic Level
P-Channel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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50 AMPERES 30 VOLTS RDS(on) = 25 mW
P-Channel D
* Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a * * * * *
Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured - Not Sheared Specially Designed Leadframe for Maximum Power Dissipation Pb-Free Packages are Available
G
S
4 D2PAK CASE 418B STYLE 2
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 MW) Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 15 20 50 31 150 125 1.0 2.5 - 55 to 150 1250 Unit Vdc Vdc Vdc Vpk Adc Apk W W/C W C mJ 1 Gate MTB50P03H A Y WW G 1 2 3
MARKING DIAGRAM & PIN ASSIGNMENT
4 Drain
M TB 50P03HG AYWW
TJ, Tstg EAS
2 Drain
3 Source
C/W RqJC RqJA RqJA TL 1.0 62.5 50 260 C
= Device Code = Assembly Location = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Preferred devices are recommended choices for future use and best overall value.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 6
Publication Order Number: MTB50P03HDL/D
MTB50P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 25 Adc) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ =125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 25 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 24 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) (VDD= 15 Vdc, ID = 50 Adc, VGS = 5.0 Vdc, RG = 2.3 W) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 50 Adc, VGS = 0 Vdc) (IS = 50 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - trr (IS = 50 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA LD LS - - 3.5 7.5 - - nH nH ta tb QRR - - - - 2.39 1.84 106 58 48 0.246 3.0 - - - - - mC ns Vdc - - - - - - - - 22 340 90 218 74 13.6 44.8 35 30 466 117 300 100 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 3500 1550 550 4900 2170 770 pF (Cpk 3.0) (Note 3) VGS(th) 1.0 - (Cpk 3.0) (Note 3) RDS(on) - VDS(on) - - gFS 15 20 - 0.83 - 1.5 1.3 mhos 20.9 25 Vdc 1.5 4.0 2.0 - Vdc mV/C mW (Cpk 2.0) (Note 3) V(BR)DSS 30 - IDSS - - IGSS - - 100 - - 1.0 10 nAdc - 26 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 15)
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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 100 VGS = 10 V 8V 80 4.5 V 6V 4V 5V I D , DRAIN CURRENT (AMPS) 80
TJ = 25C
VDS 5 V
TJ = - 55C 25C 100C
60
60
3.5 V 40 3V 20 2.5 V 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
40
20 0 1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.029 VGS = 5 V 0.027 0.025 0.023 25C 0.021 0.019 0.017 0.015 0 20 40 - 55C TJ = 100C
0.022 TJ = 25C 0.021 0.020 0.019 0.018 0.017 10 V 0.016 0.015 0 20 40 60 80 100 VGS = 5 V
60
80
100
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
1.35 VGS = 5 V ID = 25 A I DSS, LEAKAGE (nA)
1000 VGS = 0 V
1.25
TJ = 125C 100
1.15
1.05
0.95 100C 0.85 - 50 10 - 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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MTB50P03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
14000
VDS = 0 V Ciss 12000
VGS = 0 V
TJ = 25C
C, CAPACITANCE (pF)
10000 8000 Crss 6000 4000 2000 0 10 5 VGS 0 VDS 5 Ciss Coss Crss 10 15 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB50P03HDL
6 QT 5 Q1 4 3 2 1 Q3 0 0 10 20 30 40 50 60 VDS 70 QT, TOTAL GATE CHARGE (nC) ID = 50 A TJ = 25C Q2 VGS 25 20 15 10 5 0 80 30 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 30 V VGS = 10 V ID = 50 A TJ = 25C
tr tf
t, TIME (ns)
td(off) 100
td(on)
10
1 RG, GATE RESISTANCE (Ohms)
10
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
50 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 40
high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
30
20
10 0 0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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MTB50P03HDL
di/dt = 300 A/ms I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
I D , DRAIN CURRENT (AMPS)
VGS = 20 V SINGLE PULSE TC = 25C 100 100 ms 1 ms 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
1000
1400 1200 ID = 50 A
1000 800 600 400 200 0 25 50 75 100 125 150
1 0.1
100
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t1 t2 DUTY CYCLE, D = t1/t2 1.0E-01 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
Figure 14. Thermal Response
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 IS
RqJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils
di/dt IS trr ta tb TIME tp 0.25 IS
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (C)
Figure 15. Diode Reverse Recovery Waveform
Figure 16. D2PAK Power Derating Curve
ORDERING INFORMATION
Device MTB50P03HDL MTB50P03HDLG MTB50P03HDLT4 MTB50P03HDLT4G Package D2PAK D2PAK (Pb-Free) D2PAK D2PAK (Pb-Free) 800 / Tape & Reel 50 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MTB50P03HDL
PACKAGE DIMENSIONS
D2PAK 3 CASE 418B-04 ISSUE J
C E -B-
4 DIM A B C D E F G H J K L M N P R S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B-01 THRU 418B-03 OBSOLETE, NEW STANDARD 418B-04. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40
V W
A
1 2 3
S
-T-
SEATING PLANE
K G D 3 PL 0.13 (0.005) H
M
W J
TB
M
VARIABLE CONFIGURATION ZONE L M
R
N U L
P L M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
M
F VIEW W-W 1
F VIEW W-W 2
F VIEW W-W 3
SOLDERING FOOTPRINT*
8.38 0.33
10.66 0.42
1.016 0.04
5.08 0.20
3.05 0.12 17.02 0.67
SCALE 3:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MTB50P03HDL
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MTB50P03HDL/D

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